Field of the Invention
The present invention relates to a bus architecture communications scheme for enabling baseband data communications between a plurality of interconnected devices or nodes in a computer system, and more particularly, to a bus transceiver incorporating a high speed, binary transfer mode with a low speed, ternary control transfer mode having a full duplex dominant logic scheme for bi-directional, simultaneous signal transfer.
Hereinafter, all computer devices will be referred to as "nodes" for simplicity irregardless of whether or not the specific device has a higher intelligence otherwise known as a "local host". In addition, the term local host will be used irregardless of whether or not it comprises hardware or hardware and software.
Nodes within a computer system, such as a disk drive, a CRT, a printer and the like, need the ability to convey signals between themselves. In the past, this has been accomplished by means of a standard I/O bus which comprises a plurality of transmission lines or channels and acts as a shared communications path for interconnecting several nodes in the system. In such a system, it is desirable to provide a bus architecture in which signals can be simultaneously transmitted between nodes connected to the bus in order to increase the volume of information that can be transmitted in a given time period, thereby increasing the over-all speed of the computer. This type of transmission is known as full-duplex transmission. In conventional bus architectures, however, a signal transmitted on the bus by a particular node is available for reception by all other nodes attached to the bus so that if two or more signals were simultaneously transmitted on the bus, they would superimpose to create a garbled signal un-intelligible to any node.
In conventional baseband data communication systems, this problem has been partially overcome by the following two techniques. The first technique is known as time duplexing wherein a plurality of nodes connected to a shared I/O bus are individually given a specific allotment of time to transmit their signals on the bus. This type of transmission resembles a round robin procedure in which each node is sequentially given access to the bus. A major drawback with the use of time duplexing on a shared bus is that it requires a general synchronization system to sequentially enable the driver of each node for a certain time, and even then, the over-all transmission is slow since the signals are still individually transmitted. Furthermore, this type of transmission is not bi-directional (i.e., full duplex) so that a node which requests information from another node must wait until the second node is given its turn to transmit the desired information.
The second technique consists of providing a bus which has at least two transmission lines for each interconnection between nodes coupled to the bus so as to enable full duplex transmission between any two of the nodes. For example, if there are four nodes coupled to each other so as to form six interconnections, twelve transmission lines would be required. Although this technique solves the problems presented by the previous technique, it creates other problems relating to the physical size and complexity of the bus and the large amount of power required to drive the bus.
Furthermore, in prior art bus architectures, data transfer busses are commonly used for the transmission of baseband data signals between nodes directly coupled to each other via point-to-point interconnections or "links" forming the bus. In this type of bus, data signal transfers between nodes occur only occasionally when one node needs to request data from or transmit data to another node. Because the bus may idle for indefinitely long periods of time between successive data transfers, it is customary to put the bus in an idle state by disabling the drivers of adjacent nodes so as to reduce the power consumption that would otherwise occur.
One method of maintaining the bus in the idle state is to use bias circuits to actively bias the bus in one of two signal states (i.e., a binary 1 or 0 signal state), however, this approach still consumes a significant amount of power due to the current required to maintain these states. Another known method for use with a differential data transfer bus is to passively bias the bus through the use of low impedance, passive termination devices. However, the use of this method to maintain the bus idle state undermines the overall common mode rejection of a double terminated, differential bus. Hence, in order to maintain the bus idle state, prior art bus architectures have traditionally required either the utilization of large amounts of power or a sacrifice in the common mode rejection range of the bus.
More recently, however, another means for reducing the power consumption caused by the bus idle state was realized through the use of a third, low power signal state as the bus idle state. This third state, known as a Z signal state, has a signal amplitude half way between the two binary signal states such that the corresponding current amplitude (when driven on the bus) is nearly 0 mA. According to the present invention, it was realized that the use of an intermediate signal state having a current amplitude of approximately 0 mA for the bus idle state would not only cause a reduction in the power consumption by the bus during an idle state, but would also provide an additional signaling state for use in implementing a full-duplex transmission scheme on the bus. Although this third state has been used in burst mode, differential busses for reducing the power consumption during the bus idle state, it has not been utilized for the transfer of data on a bus.
In an attempt by Applicants to implement the Z signal state in a burst mode, differential bus, it was found that this state constituted a special problem due to the design of conventional binary receivers utilized in such busses for the detection of the binary signal states. Specifically, a naive implementation of the intermediate Z signal state on the bus using a conventional binary receiver causes unpredictable behavior and produces erroneous signals during the bus idle state. This is due to current fluctuations on the bus about the intermediate current amplitude of the Z signal state which causes the receiver to randomly switch states between the binary signal states. According to another implementation, Applicants utilized a hysteresis receiver having a hysteresis region around the current amplitude of the Z signal state to prevent the random oscillation. However, the use of a hysteresis receiver, while absolutely mandatory during the control signal transfer phase, represented a serious problem during the data signal transfer phase where the hysteresis receiver generated adverse duty cycle distortions during normal data transmissions.
Accordingly, it is an object of the present invention to provide a method and apparatus for a bus transceiver incorporating a high speed, binary data transfer mode with a ternary control transfer mode having a full duplex dominant logic transmission scheme for automatic determination of the preferred data signal transfer direction and for the exchange of other control and identification information.
Another object of the present invention is to provide a method and apparatus for the common mode shifting of the signals received by the bus transceiver of the present invention using a PNP level shifting circuit at the front end of each the high speed, binary receiver, the low speed, ternary receiver and the preemptive signaling receiver.
A further object of the present invention is to provide a method and apparatus for a bus transceiver incorporating a high speed, binary data transfer mode with a ternary transfer mode having a full duplex dominant logic transmission scheme using a single ternary receiver comprising two voltage comparators in addition to a PNP level shifting circuit at the front end of each comparator.